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IC89C54/58/64 integrated circuit solution inc. 1 mc009-0b icsi reserves the right to make changes to its products at any time without notice in order to improve design and supply the be st possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 2000, integrated circuit solution inc. IC89C54/58/64 cmos single chip 8-bit microcontroller with 16/32/64-kbytes of flash features ? 80c52 based architecture ? 16k/32k/64k byte flash memory with fast- pulse programming algorithm ? 256 x 8 ram ? three 16-bit timer/counters ? full duplex serial channel ? boolean processor ? four 8-bit i/o ports, 32 i/o lines ? memory addressing capability C 64k program memory and 64k data memory ? program memory lock C lock bits (3) ? power save modes: C idle and power-down ? eight interrupt sources ? most instructions execute in 0.3 s ? cmos and ttl compatible ? maximum speed: 40 mhz @ vcc = 5v ? packages available: C 40-pin dip C 44-pin plcc C 44-pin pqfp general description IC89C54, ic89c58, ic89c64 are members of icsi embedded microcontroller family. the IC89C54/58/64 uses the same powerful instruction set, has the same architecture, and is pin-to-pin compatible with standard 80c52 controller devices. IC89C54/58/64 are just changed internal flash size, other features are same as standard ic89c52. the IC89C54/58/64 contains a 16k/32k/64k x 8 flash; a 256 x 8 ram; 32 i/o lines for either multi-processor communications; i/o expansion or full duplex uart; three 16-bit timers/counters; an eight-source, two-priority-level, nested interrupt structure; and on chip oscillator and clock circuit. the IC89C54/58/64 can be expanded using standard ttl compatible memory. figure 1. IC89C54/58/64 pin configuration: 40-pin dip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 t2/p1.0 t 2ex/p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 rst rxd/p3.0 txd/p3.1 int0/p3.2 int1/p3.3 t0/p3.4 t1/p3.5 wr/p3.6 rd/p3.7 xtal2 xtal1 gnd vcc p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea/vpp ale/pro g psen p2.7/a15 p2.6/a14 p2.5/a13 p2.4/a12 p2.3/a11 p2.2/a10 p2.1/a9 p2.0/a8
IC89C54/58/64 2 integrated circuit solution inc. mc009-0b top view figure 2. IC89C54/58/64 pin configuration: 44-pin plcc wr/p3.6 rd/p3.7 xtal2 xtal1 gnd nc a8/p2.0 a9/p2.1 a10/p2.2 a11/p2.3 a12/p2.4 p1.4 p1.3 p1.2 p1.1/t2ex p1.0/t2 nc vcc p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea/vpp nc ale/prog psen p2.7/a15 p2.6/a14 p2.5/a13 p1.5 p1.6 p1.7 rst rxd/p3.0 nc txd/p3.1 int0/p3.2 int1/p3.3 t0/p3.4 t1/p3.5 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 index 43 65 2144 18 19 20 21 22 23 24 43 42 41 40 25 26 27 28
IC89C54/58/64 integrated circuit solution inc. 3 mc009-0b figure 3. IC89C54/58/64 pin configuration: 44-pin pqfp wr/p3.6 rd/p3.7 xtal2 xtal1 gnd nc a8/p2.0 a9/p2.1 a10/p2.2 a11/p2.3 a12/p2.4 p1.4 p1.3 p1.2 p1.1/t2ex p1.0/t2 nc v cc p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea/vpp nc ale/prog psen p2.7/a15 p2.6/a14 p2.5/a13 p1.5 p1.6 p1.7 rst rxd/p3.0 nc txd/p3.1 int0/p3.2 int1/p3.3 t0/p3.4 t1/p3.5 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 38 12 13 14 15 16 17 18 37 36 35 34 44 43 42 41 40 39 19 20 21 22
IC89C54/58/64 4 integrated circuit solution inc. mc009-0b figure 4. IC89C54/58/64 block diagram port 1 port 0 port 2 port 3 p1[7:0] p0[7:0] p2[7:0] p3[7:0] timer 2 uart int0 int1 timer 1 timer 0 ale psen rst ea xtal2 xtal1 16k/32k/64k main code flash 256 byte ram clock & timing sfr block vss vcc 80c31 cpu core
IC89C54/58/64 integrated circuit solution inc. 5 mc009-0b table 1. detailed pin description symbol pdip plcc pqfp i/o name and function ale/ prog 30 33 27 i/o address latch enable: output pulse for latching the low byte of the address during an address to the external memory. in normal operation, ale is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. note that one ale pulse is skipped during each access to external data memory. this pin is also the program pulse input ( prog ) during flash programming. ea /v pp 31 35 29 i external access enable: ea# must be externally held low to enable the device to fetch code from external program memory locations 0000h to ffffh. if ea# is held high, the device executes from internal program memory unless the program counter contains an address grater than 3fffh/7fffh respecting to IC89C54/58 and the device always executes internal program memory in ic89c64. this is also receives the 12 v programming enable voltage (vpp) during flash programming, when 12 v programming is selected. p0.0-p0.7 39-32 43-36 37-30 i/o port 0: port 0 is an open-drain, bi-directional i/o port. port 0 pins that have 1s written to them float and can be used as high- impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. in this application, it uses strong internal pullups when emitting 1s. port 0 also receives the command and code bytes during memory program and verification, and outputs the code bytes during program verification. external pullups are required dur- ing program verification. p1.0-p1.7 1-8 2-9 40-44 i/o port 1: port 1 is an 8-bit bi-directional i/o port with internal pull- ups. port 1 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current because of the internal pullups. port 1 also receives the low-order address byte during memory program and verification. 1240i t2(p1.0) : timer/counter 2 external count input. 2341i t2ex(p1.1): timer/counter 2 trigger input. p2.0-p2.7 21-28 24-31 18-25 i/o port 2: port 2 is an 8-bit bi-directional i/o port with internal pull- ups. port 2 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. as inputs, port 2 pins that are externally pulled low will source current because of the internal pullups. port 2 emits the high order address byte during fetches from external program memory and during accesses to external data memory that used 16-bit addresses. in this application, it uses strong internal pullups when emitting 1s. during accesses to external data memory that use 8-bit addresses, port 2 emits the contents of the p2 special function register. port 2 also receives the high-order address bits from a13 to a8 and some control signals during flash programming and verification. p2.6, p2.7 are the control signals while the chip programs and erases. p2.6 is a program command strobe signal. p2.7 is a data output enable signal.
IC89C54/58/64 6 integrated circuit solution inc. mc009-0b symbol pdip plcc pqfp i/o name and function p3.0-p3.7 10-17 11, 13-19 5, 7-13 i/o port 3: port 3 is an 8-bit bi-directional i/o port with internal pull- ups. port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 3 pins that are externally pulled low will source current because of the internal pullups. port 3 also serves the special features, as listed below: 10 11 5 i rxd (p3.0): serial input port. 11 13 7 o txd (p3.1): serial output port. 12 14 8 i int0 int0 int0 int0 int0 (p3.2): external interrupt. serve as a14 during memory program and verification. 13 15 9 i int1 int1 int1 int1 int1 (p3.3): external interrupt. serve as a15 during memory program and verification. 14 16 10 i t0 (p3.4): timer 0 external input. 15 17 11 i t1 (p3.5): timer 1 external input. 16 18 12 o wr wr wr wr wr (p3.6): external data memory write strobe. control signal during memory program, verification and erase. 17 19 13 o rd rd rd rd rd (p3.7): external data memory read strobe. control signal during memory program, verification and erase. psen 29 32 26 o program store enable: the read strobe to external program memory. when the device is executing code from the external program memory, psen is activated twice each machine cycle except that two psen activations are skipped during each access to external data memory. psen is not activated during fetches from internal program memory. psen is an input control signal while memory program and verification. rst 9 10 4 i reset: a high on this pin for two machine cycles while the oscillator is running resets the device. an internal resistor to vss permits a power-on reset using only an external capacitor. a small internal resistor permits power-on reset using only a capacitor connected to vcc. rst is an input control signal during memory program and verification. xtal 1 19 21 15 i crystal 1: input to the inverting oscillator amplifier and input to the internal clock generator circuits. xtal 2 18 20 14 o crystal 2: output from the inverting oscillator amplifier. gnd 20 22 16 i ground: 0v reference. vcc 40 44 38 i power supply: this is the power supply voltage for operation. table 1. detailed pin description (continued)
IC89C54/58/64 integrated circuit solution inc. 7 mc009-0b opera tion descriptpion the detail desription of the IC89C54/58/64 included in this desription are: ? memory map and registers ? flash memory other informations refer to ic80c52/32 data sheet except flash memory. main flash ram size IC89C54 16k bytes : [0h~3fffh] 256 bytes : [ 0-ffh] ic89c58 32k bytes : [0h~7fffh] 256 bytes : [ 0-ffh] ic89c64 64k bytes : [0h~ffffh] 256 bytes : [ 0-ffh] memory map and registers table 1 shows program memory and data memory size versus three products. the IC89C54/58/64 series includes a standard ic80c32 and a 16k/32k/64k flash memory. the program memory and data memory access ranges are listed table 2. table 2. program memory and data memory sizes flash memory programming the flash architecture of IC89C54/58/64 is shown in figure 5. IC89C54/58 include block 1 and lock bits block. the signature bytes are fixed value reside in mcu, they are read only. block 2 resides in ic89c64 only. figure 5. the flash architecture of IC89C54/58/64 IC89C54 3 lock bits falsh cell dummy address 3fffh 0000h 0032h 0030h 7fffh 0000h 0032h 0030h efffh 0000h 0032h 0030h ffffh f000h 16k flash (block 1) 3x8 bits signature bytes dummy address 32k flash (block 1) 3x8 bits signature bytes 60k flash (block 1) 4k flash (block 2) 3x8 bits signature bytes 3 lock bits falsh cell 3 lock bits falsh cell ic89c58 ic89c64
IC89C54/58/64 8 integrated circuit solution inc. mc009-0b the IC89C54/58/64 provide the user with a direct flash memory access that can be used for programming into the flash memory without using the cpu. the direct flash memory access is entered using the external host mode. while the reset input (rst) is continually held active (high), if the psen pin is forced by an input with low state, the device enters the external host mode arming state at this time. the cpu core is stopped from running and all the chip i/o pins are reassigned and become flash memory access and control pins. at this time, the external host should initiate a read signature bytes operation. after the completion of the read signature bytes operation, the device is armed and enters the external host mode. after the device enters into the external host mode, the internal flash memory blocks are accessed through the re-assigned i/o port pins by an external host, such as a printed circuit board tester, a pc controlled development board or an mcu programmer. when the chip is in the external host mode, port 0 pins are assigned to be the parallel data input and output pins. port 1 pins are assigned to be the low order address bus signals for the internal flash memory (a0-a7). the first six bits of port 2 pins (p2[0:5]) are assigned to be the upper order address bus signals for the internal flash memory (a8-a13) along with two of the port 3 pins (p3.2 as a14 and p3.3 as a15). two upper order port 2 pins (p2.6 and p2. 7) and two upper order port 3 pins (p3.6 and p3.7) along with rst, psen , prog /ale, ea pins are assigned as the control signal pins. the p3.4 is assigned to be the ready/ busy status signal, the p3.5 is assigned to be the timeout signal, which can be used for handshaking with the external host during a flash memory programming operation. the flash memory programming operation (erase, program, verify, etc.) is internally self-timed and can be controlled by an external host asynchronously or synchronously. the insertion of an arming command prior to entering the external host mode by utilizing the read signature bytes operation provides additional protection for inadvertent writes to the internal flash memory cause by a noisy or unstable system environment during the power-up or power unstable conditions. the external host mode uses hardware setup mode, which are decoded from the control signal pins, to facilitate the internal flash memory erase, test and programming process. the external host mode commands are enabled on the falling edge of ale/ prog . the list in table 3 outlines all the setup conditions of normal mode. before entering these written modes must have read 3 signature bytes. programming interface some conditions must be satisfied before entering the programming mode. the conditions are listed in table 3. the interface-controlled signals are matched these conditions, then the IC89C54/58/64 will enter received command mode. the flash command is accepted by the flash command decoder in command received mode. the programming interface is listed in figure 6. figure 6. ic89c52/54/64 external host programming signals vss rst psen ale/prog ea/vpp h l prog pulse 12v/h vcc IC89C54/58/64 10k vcc d7-d0 p0 a7-a0 p3.4 p3.5 p2.6 p2.7 p3.6 p3.7 ready/busy timeout p2.6 p2.7 p3.6 p3.7 a13-a8 a15-a14 p1 p2.5-2.0 p3.3-3.2
IC89C54/58/64 integrated circuit solution inc. 9 mc009-0b mode(1) rst psen# prog# ea# p2.6 p2.7 p3.6 p3.7 p0[7:0] p1[7:0] p3[3:2] com p2[5:0] hex(3) read signature byte h l h h l l l l do al ah 0 chip erase h l 12v/h h l l l xxx1 block 1 (2) erase h l 12v/h l h l l xxx2 block 2 (2) erase h l 12v/h l l h l xxx4 program main code h l 12v/h l h h h di al ah e program lock bit 1 h l 12v/h h h h h x x x f program lock bit 2 h l 12v/h h h l l xxx3 program lock bit 3 h l 12v/h h l h l xxx5 verify lock bits h l h h h l l h do[3:1] x x 9 verify main code h l h h l l h h do al ah c 1. to read the signature bytes 30h, 31h, 32h are needed before any written command. to read signature bytes is needed after any new mode changed. this operation provides additional protection for inadvertent writes to the internal flash memory cause by a noisy or unstable system environment during the power-up or unstable power condition. if any unstable power condition has happened while written operation proceeds, to read signature bytes again will re-enable written command. (power-on reset voltage is about 2.7v.) 2. block 1 includes flash address from 0000h to 3fffh in IC89C54, from 0000h to 7fffh in ic89c58, from 0000h to efffh in ic89c64. block 2 includes f000h to ffffh. block 2 is resident in ic89c64 only. 3. com hex presents the combination value of [p3.7, p3.6, p2.7, p2.6]. product identification the read signature bytes command accesses the signature bytes that identify the device as IC89C54/58/64 and the manufacturer code. external programmers primarily use these signature bytes, shown in table 4, in the selection of programming algorithms. the read signature bytes command is selected by the byte code of 00h on p3[7:6] and p2[7: 6]. manufacturer code of icsi is d5h that reside in address 30h of signature. the flash memory sizes of mcu are shown in address 31h, code value 04h respect to 16k main flash memory, code value 08h respect to 32k main flash memory, code value 10h respect to 64k main flash memory. the address 32h value of signature byte respect to written operation vpp value, code value ffh respects to 12v and 55h respects to 5v. table 4. signature bytes information addr 30h addr 31h addr 32h IC89C54 (vpp=12v) d5h 04h ffh IC89C54 (vpp=5v) d5h 04h 05h ic89c58 (vpp=12v) d5h 08h ffh ic89c58 (vpp=5v) d5h 08h 05h ic89c64 (vpp=12v) d5h 10h ffh ic89c64 (vpp=5v) d5h 10h 05h table 3. flash programming mode
IC89C54/58/64 10 integrated circuit solution inc. mc009-0b arming command an arming command must take place before a written mode will be recognized by the IC89C54/58/64. this is to prevent accidental triggering of written operation due to noise or programmer error. the arming command is as follows: a read signature bytes command is issued. this is actually a natural step for the programmer, but will also serve as the arming command. after the above sequence, all other written mode commands are enabled. before the read signature bytes command is received, all other written mode commands received are ignored. the IC89C54/8/64 will exit written mode if power off, so arming command is needed every power on for entering external host command mode. external host mode commands the following is a brief description of the commands. see table 3 for all signal logic assignments for the external host mode commands. the critical timing for all erase and program commands, is self-generated by the flash memory controller on-chip. the high-to-low transition of the prog signal initiates the erase and program commands, which are synchronized internally. all the data in the memory array will be erased to ffh. memory addresses that are to be programmed must be in the erased state prior to programming. there are two erase commands in ic89c64, block 1 erase and block 2 erase. selection of the erase command to use, prior to programming the device, will be dependent upon the contents already in the array and the desired programming field block. the chip erase command erases all bytes in both memory blocks (16k/32k/64k) of the IC89C54/58/64.this command ignores the lock bits status and will erase the security byte. the chip erase command is selected by the byte code of 01h on p3[7:6] and p2[7:6]. the block 1 erase command erases all bytes in one of the memory blocks 1 (16/32/60k) of the IC89C54/58/64. the block 2 erase command erases all bytes in one of the memory blocks 2 (address range is from f000h to ffffh) of the ic89c64. these block erase commands will not enable if the lock bit 2 or lock bit 3 is enabled. flash operation status detection (ext. host handshake) the IC89C54/58/64 provide two signals mean for an external host to detect the completion of a flash memory operation, therefore the external host can optimize the system program or erase cycle of the embedded flash memory. the end of a flash memory operation cycle (erase or program) can be detected by: 1) monitoring the ready/ busy bit at port 3.4; 2) monitoring the timeout polling bit at port 3.5. the following two program com- mands are for programming new data into the memory array. selection of which program command to use for programming will be dependent upon the desired pro- gramming field size. the program commands will not enable if lock bit 2 or lock bit 3 is enabled on the selected memory block. the program main code command program data into a single byte. ports p0[0:7] are used for data in. the memory location is selected by p1[0:7], p2[0:5], and p3[2:3] (a0-a15). the verify main code command allows the user to verify that the IC89C54/58/64 correctly performed an erase or program command. ports p0[0:7] are used for data out. the memory location is selected by p1[0:7], p2[0:5], and p3 [2:3] (a0-a15). these commands will not enable if any lock bit is enabled on the selected memory block. ready/ b b b b b usy usy usy usy usy the progress of the flash memory programming can be monitored by the ready/ busy output signal. the ready/ busy indicates whether an embedded algorithm in written state machine (wsm) is in progress or complete. the ry/ by status is valid after the falling edge of the programming or erase controlled signal. if the output is low (busy), the device is in an erasing/programming state with an internal verification. if the output is high, the device is ready to read data. while the ry/ by signal is at low level (busy) and timeout is high level, the programming or erasing procedure is failed.
IC89C54/58/64 integrated circuit solution inc. 11 mc009-0b program lock bits protection type lb1 lb2 lb3 1 u u u no program lock feature enabled. 2 p u u movc instructions executed from external program memory are disabled from fetching code bytes from internal memory, #ea is sampled and latched on reset, and data verification is disabled. (verify signature byte and verify lock bits are still enabled.) 3p p u same as 2, also further written operation of the flash is disabled 4p p p same as 3, also external execution is disabled timeout timeout indicates whether the program or erase time has exceeded a specified internal timer limit. under these conditions timeout go to high and ready/ busy remains a low. this is a failed condition that indicates the program or erase cycle was not successful completed. if there are any program or erase failure in erasing operation, timeout go to high and ready/ busy remains low. it is cleared by any rising edge of written signal (like program main code, chip erase, etc.). the time from written signal to timeout=1 is re-initiated at every written signals rising edge. it is high when the program or erase operations dont complete and have no newly written signal in the expected time. programming a IC89C54/58/64 to program new data into the memory array, supply 5 volts to vdd and rst, and perform the following steps. 1. set rst to high and psen to low. 2. raise ea high (either 12v or 5v). 3. read the read signature bytes command to ensure the correct programming algorithm. 4. verify that the memory blocks for programming are in the erased state, ffh. if they are not erased, then erase them using the appropriate erase command. 5. set p2.6, p2.7, p3.6, p3.7 to a properly programming combination. 6. select the memory location using the address lines (p1 [0:7], p2[0:5], p3[2:3]). 7. present the data in on p0[0:7]. 8. pulse ale/ prog . 9. wait for low to high transition on ready/ busy (p3.4) or timeout pin(p3.5). if ready/ busy is from low to high, this address is programmed completely. if the timeout signal is from low to high before ready/ busy goes high, this byte is failed in programming. 10. repeat steps 6~9 until programming is finished. lock bits features the IC89C54/58/64 provide three lock bits to protect the embedded program against software piracy. these three bytes are user programmable. the relation between lock bits status and protection type are listed in table 5. table 5. lock bits features
IC89C54/58/64 12 integrated circuit solution inc. mc009-0b absolute maximum ratings notes : 1. operating temperature is for commercial product defined by this spec. 2. minimum d.c. input voltage is -0.5 v. during transitions, inputs may undershoot, to -2.0 v for periods less than 20 ns. maximum d.c. voltage on output pins is vcc+0.5 v, which may overshoot to vcc + 2.0 v for periods less than 20 ns. warning: stressing the device beyond the absolute maximum rating may cause permanent damage. this is stress rating only. operation beyond the operating conditions is not recommended and extended exposure beyond the operating conditions may affect device reliability. operating range parameter rating unit operating temperature under bias 0 to +70 c (1) storage temperature range -65 to +125 c voltage on any other pin to vss -2.0 to +7.0 v (2) power dissipation ( based on package heat transfer l imitations, not device power consumption) 1.5 w operating ranges define those limits between which the functionality of the device is guaranteed. commercial devices case temperature 0 to +70 c vcc supply voltage +4.5 to 5.5 v oscillator frequency 3.5 to 40 mhz
IC89C54/58/64 integrated circuit solution inc. 13 mc009-0b dc characteristics (ta=0c to 70c; vcc=5v +10%; vss=0v ) symbol parameter test conditions min max unit v il input low voltage (all except ea ) C0.5 0.2vcc C 0.1 v v il 1 input low voltage ( ea ) C0.5 0.2vcc C 0.3 v v ih input high voltage 0.2vcc + 0.9 vcc + 0.5 v (all except xtal 1, rst) v ih 1 input high voltage (xtal 1) 0.7vcc vcc + 0.5 v v sch + rst positive schmitt-trigger 0.7vcc vcc + 0.5 v threshold voltage v sch C rst negative schmitt-trigger 0 0.3vcc v threshold voltage v ol (1) output low voltage iol = 100 a 0.3 v (ports 1, 2, 3) i ol = 1.6 ma 0.45 v i ol = 3.5 ma 1.0 v v ol 1 (1) output low voltage i ol = 200 a 0.3 v (port 0, ale, psen )i ol = 3.2 ma 0.45 v i ol = 7.0 ma 1.0 v v oh output high voltage i oh = C10 a 0.9vcc v (ports 1, 2, 3, ale, psen ) vcc = 4.5v-5.5v i ol = C25 a 0.75vcc v i ol = C60 a 2.4 v v oh 1 output high voltage i oh = C80 a 0.9vcc v (port 0, ale, psen ) vcc = 4.5v-5.5v i oh = C300 a 0.75vcc v i oh = C800 a 2.4 v i il logical 0 input current (ports 1, 2, 3) v in = 0.45v C50 a i li input leakage current (port 0) 0.45v < v in < vcc C10 +10 a i tl logical 1-to-0 transition current v in = 2.0v C650 a (ports 1, 2, 3) r rst rst pulldown resister v in =0v 50 300 k ? note: 1. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10 ma maximum i ol per 8-bit port port 0: 26 ma ports 1, 2, 3: 15 ma maximum total i ol for all output pins: 71 ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink greater than the listed test conditions. 2.the icc test conditions are shown below. minimum vcc for power down is 2 v.
IC89C54/58/64 14 integrated circuit solution inc. mc009-0b power supply characteristics symbol parameter test conditions min max unit icc power supply current (1) vcc = 5.0v active mode 12 mhz 20 ma 16 mhz 26 ma 20 mhz 32 ma 24 mhz 38 ma 32 mhz 50 ma 40 mhz 62 ma idle mode 12 mhz 5 ma 16 mhz 6 ma 20 mhz 7.6 ma 24 mhz 9 ma 32 mhz 12 ma 40 mhz 15 ma power-down mode v cc = 5v 50 a note: 1. see figures7,8,9, and 10 for icc test conditiions. figure 7. active mode figure 8. active mode figure 9. active mode xtal1 gnd nc rst vcc p0 ea vcc vcc clock signal icc xtal2 vcc xtal1 gnd nc rst vcc p0 ea vcc vcc clock signal icc xtal2 xtal1 gnd nc rst vcc p0 ea vcc vcc icc xtal2
IC89C54/58/64 integrated circuit solution inc. 15 mc009-0b figure 10. clock signal waveform for i cc tests in active and idle mode (t clch =t chcl =5 ns) ac characteristics (ta=0c to 70c; vcc=5v +10%; v ss =0v; c1 for port 0, ale and psen outputs=100pf; c1 for other outputs=80pf) external memory characteristics 24 mhz 40 mhz variable oscillator clock clock (3.5 - 40 mhz) symbol parameter min max min max min max unit 1/t clcl oscillator frequency 3.5 40 mhz t lhll ale pulse width 68 35 2t clcl C15 ns t avll address valid to ale low 26 10 t clcl C15 ns t llax address hold after ale low 31 15 t clcl C10 ns t lliv ale low to valid instr in 147 80 4t clcl C20 ns t llpl ale low to psen low 31 15 t clcl C10 ns t plph psen pulse width 110 60 3t clcl C15 ns t pliv psen low to valid instr in 105 55 3t clcl C20 ns t pxix input instr hold after psen 0 0 0 ns t pxiz input instr float after psen 37 20 t clcl C5 ns t aviv address to valid instr in 188 105 5t clcl C20 ns t plaz psen low to address float 10 10 10 ns t rlrh rd pulse width 230 130 6t clcl C20 ns t wlwh wr pulse width 230 130 6t clcl C20 ns t rldv rd low to valid data in 157 90 4t clcl C10 ns t rhdx data hold after rd 0 0 0 ns t rhdz data float after rd 78 45 2t clcl C5 ns t lldv ale low to valid data in 282 165 7t clcl C10 ns t avdv address to valid data in 323 190 8t clcl C10 ns t llwl ale low to rd or wr low 105 145 55 95 3t clcl C20 3t clcl +20 ns t avwl address to rd or wr low 146 80 4t clcl C20 ns t qvwx data valid to wr transition 26 10 t clcl C15 ns t whqx data hold after wr 31 15 t clcl C10 ns t rlaz rd low to address float 0 0 0 ns t whlh rd or wr high to ale high 26 57 10 40 t clcl C15 t clcl +15 ns 0.45v vcc ? 0.5v t chcx t clcl t clch t clcx t chcl 0.7vcc 0.2vcc ? 0.1
IC89C54/58/64 16 integrated circuit solution inc. mc009-0b serial port timing: shift register mode 24 mhz 40 mhz variable oscillator clock clock (3.5-40 mhz) symbol parameter min max min max min max unit t xlxl serial port clock cycle time 490 510 290 310 12t clcl C10 12t clcl +10 ns t qvxh output data setup to 406 240 10t clcl C10 ns clock rising edg1 t xhqx output data hold after 73 40 2t clcl C10 ns clock rising edge t xhdx input data hold after 0 0 0 ns clock rising edge t xhdv clock rising edge to 417 250 10t clcl ns input data valid external clock drive characteristics symbol parameter min max unit 1/t clcl oscillator frequency 3.5 40 mhz t chcx high time 10 ns t clcx low time 10 ns t clch rise time 10 ns t chcl fall time 10 ns
IC89C54/58/64 integrated circuit solution inc. 17 mc009-0b flash program/erase and verification characteristics symbol parameter min max unit vpph programming and erase enable voltage 11.5 12.5 v vppl programming and erase enable voltage 4.5 6.0 v ipph programming and erase enable current while vpp=vpph - 2.0 ma ippl programming and erase enable current while vpp=vppl - 1.0 ma twscv power setup to command setup low 10 - ms tcvqv command valid to data output valid - 60 ns tavqv address valid to data output valid - 60 ns tcvpl command valid to prog# low 30 - ns tshpl vpp setup to prog# low 30 - ns tavpl address setup to prog# low 30 - ns tdvpl data setup to prog# low 30 - ns tplbl prog# low to busy# low 1 10 us tpltl prog# low to timeout low - 30 ns tblcx command hold after busy# low 30 - ns tblax address hold after busy# low 30 - ns tblph busy# low to prog# high 30 - ns tbldx data hold after busy# low 30 - us tblbh busy# low to busy# high 15 480 us tblth busy# low to timeout high 180 720 us tbhsl vpp hold after busy# high 1 - us taxqx output hold after address release 0 - ns tcxqx output hold after command release 0 - ns tblbhe busy# time while chip erase - 4.5 sec tblbhe1 busy# time while block 1 erase (IC89C54) - 1.2 sec tblbhe2 busy# time while block 1 erase (ic89c58) - 2.4 sec tblbhe3 busy# time while block 1 erase (ic89c64) - 4.0 sec tblbhe4 busy# time while block 2 erase (ic89c64) - 0.7 sec tblthe busy# low to timeout high while chip erase 0.00018 6.75 sec tblthe1 busy# low to timeout high while block 1 erase (IC89C54) 0.00018 1.8 sec tblthe2 busy# low to timeout high while block 1 erase (ic89c58) 0.00018 3.6 sec tblthe3 busy# low to timeout high while block 1 erase (ic89c64) 0.00018 6.0 sec tblthe4 busy# low to timeout high while block 2 erase (ic89c64) 0.00018 1.05 sec
IC89C54/58/64 18 integrated circuit solution inc. mc009-0b figure 11. external program memory read cycle figure 12. external data memory read cycle timing waveforms t lhll ale t avll t llpl t plph t pliv t llax t plaz t pxiz t pxix a7-a0 instr in a7-a0 t lliv t aviv psen port 0 port 2 a15-a8 a15-a8 t lldv t avll a7-a0 from ri or dpl instr in a7-a0 from pcl t avwl t avdv psen port 0 port 2 ale rd data in a15-a8 from dph a15-a8 from pch t whlh t llwl t llax t rlaz t rldv t rhdz t rhdx t rlrh
IC89C54/58/64 integrated circuit solution inc. 19 mc009-0b figure 13. external data memory write cycle figure 14. shift register mode timing waveform t avll a7-a0 from ri or dpl instr in a7-a0 from pcl t avwl psen port 0 port 2 ale wr data out a15-a8 from dph a15-a8 from pch t whlh t llwl t llax t qvwx t whqx t wlwh instruction ale clock data out data in t xlxl t xhqx t qvxh t xhdv t xhdx valid valid valid valid valid valid valid valid set ti set ri 78 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
IC89C54/58/64 20 integrated circuit solution inc. mc009-0b figure 15. read signature bytes timing(arming command) p3[7:6] p2[7:6] prog vcc t cvqv 00h 30h 31h p3[3:2] p2[5:0] p1[7:0] p0[7-0] vpp t wscv d5h 04h/08h/10h 05h/ffh t avqv t avqv t avqv 32h
IC89C54/58/64 integrated circuit solution inc. 21 mc009-0b figure 16. programming timing p3[7:6] p2[7:6] p3.5 vpp t cvpl t blcx t plbl t blbh t shpl t bhsl t blax t cqcv t slcv t cxqx 0ch/0dh (2) 0eh (1) p3[3:2] p2[5:0] p1[7:0] prog p0[7-0] p3.4(busy) t avpl t pltl t blth t bldx t avqv t axqx valid address (3) valid address (3) t blph t dvpl valid data (4) valid data 1. 0eh is for code memory programming. in lock bits programming, 0fh, 03h, 05h, respect to lock bits 1, 2, 3. 2. 0ch is for code memory verification and 0dh is for concurrent memory verification. 09h is for lock bits verification. 3. address dont care while lock bits programming or verification. 4. data dont care while lock bits programming.
IC89C54/58/64 22 integrated circuit solution inc. mc009-0b figure 17. erasing timing p3[7:6] p2[7:6] p3.5 vpp t cvpl t blcx t plbl t blbhe t blbhen t shpl t bhsl t cqcv t slcv t cxqx 0ch/0dh (2) 01h/02h/04h (1) p3[3:2] p2[5:0] p1[7:0] prog p0[7-0] p3.4(busy) t pltl t blthe t blthen t avqv t axqx valid address (3) t blph valid data 1. 01h/02h/04h are for chip erase/block 1 erase/block 2 erase. 2. 0ch is for code memory verification and 0dh is for concurrent memory verification. 09h is for lock bits verification.
IC89C54/58/64 integrated circuit solution inc. 23 mc009-0b figure 18. test mode entering timing figure 19. external clock drive waveform figure 20. ac test point note: 1.ac inputs during testing are driven at vcc-0.5v for logic 1 and 0.45v for logic 0. timing measurements are made at vih min for logic 1 and max for logic 0. 0.45v vcc ? 0.5v t chcx t clcl t clch t clcx t chcl 0.7vcc 0.2vcc ? 0.1 vcc - 0.5v 0.45v 0.2vcc + 0.9v 0.2vcc - 0.1v t cvsl t phch t slsh 1st stage test mode enable 2rd stage test mode enable 59h 59h 89h 89h p2.6 p0[7-0] 1. ea#, prog#, p3.7, p2.7 are high level; p3.6 is low level.
IC89C54/58/64 24 integrated circuit solution inc. mc009-0b ordering information commercial range: 0c to +70c speed order part number package 12 mhz IC89C54/58/64-12pl plcc IC89C54/58/64-12w 600mil dip IC89C54/58/64-12pq pqfp 24 mhz IC89C54/58/64-24pl plcc IC89C54/58/64-24w 600mil dip IC89C54/58/64-24pq pqfp 40 mhz IC89C54/58/64-40pl plcc IC89C54/58/64-40w 600mil dip IC89C54/58/64-40pq pqfp integrated circuit solution inc. headquarter: no.2, technology rd. v, science-based industrial park, hsin-chu, taiwan, r.o.c. tel: 886-3-5780333 fax: 886-3-5783000 branch office: 7f, no. 106, sec. 1, hsin-tai 5 th road, hsichih taipei county, taiwan, r.o.c. tel: 886-2-26962140 fax: 886-2-26962252 http://www.icsi.com.tw

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